1. Field of the Invention
The present invention generally relates to clock or timing circuits, and more particularly to a method of operating a memory array such as static, random-access memory (SRAM) which uses locally generated clock signals.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells, memory cells and input/output (I/O) cells.
Power usage has become a dominant concern in the development of integrated circuits for data processing systems. Low power circuits are becoming more prevalent due to power consumption problems. Low power designs are also preferable since they exhibit less power supply noise and can provide better tolerance with regard to manufacturing variations. Excess power usage is not only costly and inefficient, but also leads to heat management problems. Power dissipation has become a limiting factor for the yield of high-performance circuit designs (operating at frequencies around 1 gigahertz or more) with deep submicron technology. Modern microprocessor designs are accordingly dictated by the power constraint.
Clock nets between cells can contribute up to 50% of the total active power in multi-GHz designs. The power constraint thus presents an additional challenge for the designer in constructing a clock network for the cells, and this challenge is becoming more difficult with the latest technologies like low-power, 65-nanometer integrated circuits. There are several techniques for minimizing power while still achieving timing objectives for high performance, low power systems. One method involves the use of local clock buffers (LCBs) to distribute the clock signals. A typical clock control system has a clock generation circuit (e.g., a phase-lock loop) that generates a master clock signal which is fed to a clock distribution network that renders synchronized global clock signals at the LCBs. Each LCB adjusts the global clock duty cycle and edges to meet the requirements of respective circuit elements, e.g., local logic circuits, latches or memory arrays. Placing LCBs close to clocked circuits also reduces clock skew which helps improve the timing of the circuit.
Another approach to power management is dynamic voltage scaling where the voltage used in a given component is increased or decreased depending upon operational, process or environmental parameters. Dynamic voltage scaling is an efficient way to reduce both static and dynamic power, but a wide range of voltage is required to maintain proper operation of a circuit under different performance specifications, and different power/delay metrics typically have different optimum power supply voltages (Vdd).
The use of different voltages for different cells in a circuit combined with dynamic voltage scaling presents unique problems, especially with low voltage operations, since the delays of different cells scale differently at low voltages. For example, a static, random-access memory (SRAM) array which uses locally generated clock signals from an LCB may have a device threshold voltage (Vth) of 0.5 volts while the LCB operates at a device threshold voltage of 0.4 volts (memory typically has a higher Vth for robustness and low leakage, and the peripheral control signal generation circuits have a lower Vth for high speed operation). The delay in the SRAM will scale differently with varying voltage than the delay in the logic gates of the LCB due to wire loading in the SRAM versus device loading in the logic gates. This delay differential can be significant, negatively impacting manufacturing requirements and/or circuit performance.
Some circuits have a high sensitivity to variations at low voltage. In the example of SRAM control, the LCB generates a local clock signal and a delayed local clock signal which are buffered to generate the wordline, precharge and latching signals. The delayed local clock signal is obtained by delaying and extending the pulse width of the local clock signal using inverter chains. The most critical timing component in the SRAM control is the local clock signal pulse width which determines SRAM read and write time windows. However, it is very difficult to control this timing component with dynamic voltage scaling because of variations in inverter delay with changes in supply voltage and differences between threshold voltages. As a result the SRAM delay function does not track the LCB inverter delay function.
One potential solution to this problem is the use of programmable delay circuits, such as that described in U.S. Pat. No. 5,389,843. A series of multiplexers and delay elements are used to output a signal having an adjustable delay. A digital input value having N number of programmable bits is used to control the N delay stages of the circuit, that is, the bits are respective selectors for the multiplexers. While the number of delay elements may be selectively programmed with this circuit, there are still variations in the actual delay of these elements with respect to supply voltage which are only imprecisely known, so this approach is not feasible for devices that are particularly sensitive at low voltages.
Another solution is the use of “dummy” circuits to replicate the delay path. This approach is applied to memory control in U.S. Pat. Nos. 5,596,539 and 6,760,269. Sense amplifiers connected to dummy bit lines drive control lines that assert the memory array timing signals when a dummy cell has finished a read operation to provide precise data read timing. While this approach provides a real-time basis for delay adjustment, the delay variation of the replicated SRAM path may not match the delay variation in the LCB logic as explained above, resulting in poor timing control.
In light of the foregoing, it would be desirable to devise an improved method of calibrating local clock signals for sensitive circuits such as memory arrays. It would be further advantageous if the method could take into consideration both variations in delay due to power supply voltage and differences between threshold voltages for related circuit components.